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Technical Brief 457
ISL6116 (+5V)
Figures 1 and 2 show the ISL6116 in an ISL6115 high side
switch application eval board. Jumper JP1 is removed from
the original configuration so a +5V Power Source can be
applied to B2. +12V is needed to bias the IC and is applied
at B1. The overcurrent set point is 1.5A.
In Figure 3, notice the soft-start ramp up of GATE after
PWRON is initiated, thus allowing the gradual ramp up of
I LOAD . In Figure 4, starting up into a short is shown. Upon
PWRON being asserted, CTIM is immediately begins
ISL6116 (+5V) Figures
charging. The nominal time-out period is CTIM x 93k ? . An
overcurrent (OC) event occurs when the current through the
sense resistor exceeds the user programmed OC threshold
(see data sheet). The controller enters current regulation
(CR) and capacitor CTIM begins charging. The nominal
time-out period is CTIM x 93k ? . (see Figure 5A). A transient
event from 500mA to 1A occurs. PGOOD is pulled low due
to a temporary undervoltage condition occurring on +5V OUT ,
but CTIM stays low as a true OC event never occurs (See
Figure 5B).
+
B3
LOAD
B4
-
+5V
R2
1
8
PWRON
R1
2
ISL6116
7
PGOOD
R5
Q1
R3
3
4
U1
C3
6
5
D1
R4
C2
D2
DD1
3.3V
C1
B5
+5V
V+ B2
JP1
+12V
V BIAS
B1
FIGURE 1. EVAL BOARD SCHEMATIC
I CR = 1.5A
Ch3 PGOOD
Ch2 PWRON
FIGURE 2. EVAL BOARD PICTURE
I CR = 1.5A
Ch2 CTIM
Ch4 I LOAD
Ch1 GATE
Ch1 GATE
Ch4 I LOAD
Ch3 PGOOD
FIGURE 3. TURN ON VIA PWRON INTO NOMINAL LOAD
2
FIGURE 4. TURN ON VIA PWRON INTO SHORT
TB457.0
April 18, 2006
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